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SystemC
SystemVerilog
uvm_reg
  • Create powerful for loops
    2025-05-16
    The Power of "define ... as computed"
    'e' Language
    The Power of "define ... as computed"
  • Design Verification with SystemVerilog/UVM
    2025-03-11
    Course: Design Verification with SystemVerilog/UVM
    SystemVerilog   UVM   uvm_reg   Verification
    Course: Design Verification with SystemVerilog/UVM
  • Open letter to future verification engineers
    2023-07-18
    Verification Is All About ... Trust
    'e' Language   SystemVerilog   UVM   uvm_reg   Verification   vr_ad
    Verification Is All About ... Trust
  • Avoid terminating a task when it's process is killed
    2023-02-08
    How to Decouple Threads in SystemVerilog
    SystemVerilog   UVM
    How to Decouple Threads in SystemVerilog
  • Gray Zone Comparison Proper Configuration
    2022-12-07
    The Hidden Feature of vr_ad: Gray Zone Comparison
    'e' Language   vr_ad
    The Hidden Feature of vr_ad: Gray Zone Comparison
  • SystemVerilog Tip: How to Do Logging in UVM
    Assign multiple IDs to the same message
    2022-09-21
    SystemVerilog Tip: How to Do Logging in UVM
    SystemVerilog   UVM
    SystemVerilog Tip: How to Do Logging in UVM
  • How temporal expressions evaluation works
    2022-08-15
    How to Miss Events in Specman
    'e' Language
    How to Miss Events in Specman
  • How to Handle Data Coming From Parallel Threads
    Associate a Priority to Data Coming From Paralel Threads
    2022-07-22
    How to Handle Data Coming From Parallel Threads
    SystemVerilog
    How to Handle Data Coming From Parallel Threads
  • How to configure vr_ad library
    2022-06-01
    How to Startup vr_ad e Library
    'e' Language   vr_ad
    How to Startup vr_ad e Library
  • The Strange Ways of Specman’s Return Statement
    Learn how return statement works with method extensions
    2022-04-12
    The Strange Ways of Specman's Return Statement
    'e' Language
    The Strange Ways of Specman's Return Statement
  • How to Use UVM Callbacks With Configuration Fields
    UVM callbacks in configuration fields
    2022-03-07
    How to Use UVM Callbacks With Configuration Fields
    SystemVerilog
    How to Use UVM Callbacks With Configuration Fields
  • How to Access Protected Fields in SystemVerilog
    2021-09-01
    How to Access a Protected Property or Method in SystemVerilog
    SystemVerilog
    How to Access a Protected Property or Method in SystemVerilog