Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their phone some movie, you will know that you worked on that chip which streamed the movie so seamlessly […]
Verifying RTL updatable registers (e.g. status registers) can be very difficult due to factors like slight desynchronization between model and DUT or different sampling points for the register value. Register reads in the out-of-synch window produce false errors which are a nightmare to handle in the verification environment. Luckily, the vr_ad library comes with a […]
In ‘e’ language events are heavily used for all kinds of jobs, from coverage collection, to TCMs synchronization or even passing data between two entities (a reminiscence from the times when the concept of ports was not yet introduced). The syntax for declaring an event in ‘e’ is pretty straight forward: One of the most […]
In this post I will describe all the steps I take to startup the vr_ad register model, implemented in e language. If you do things differently please share your view in the comments section below. If you want to see what is the equivalent of this in SystemVerilog, with UVM library, have a look at this […]
‘e’ language is an Aspect Oriented Programming (AOP) language with a lot of awesome features. One of this features is the ability to extend methods with one of the following statements: is also is first is only In this article we’ll see the strange way in which Specman’s return statement behaves with this very nice […]
Even though ‘e’ language documentation is quite well written, there are still some stuff either not described in the specifications, or described in just a few words. That’s a pity since, over time, I found out a lot of useful undocumented features of ‘e’ language. The first one that I want to share with you […]
One too many times I’ve seen great verification engineers, experts in ‘e’ language programming, afraid of moving towards SystemVerilog. Their fears covered the full spectrum: from online myths to extremely well founded arguments. Regardless of how well or not is the argument, times are changing and we need to keep up with the technologies. One […]
