SystemVerilog | | CFS Vision

Mar 11

Course: Design Verification with SystemVerilog/UVM

Posted by Cristian Slav

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I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how they can be applied effectively in verification environments. Verification Environment Creation: Learn the step-by-step process of building a robust verification environment from the ground up using […]

Jul 18

Verification Is All About … Trust

Posted by Cristian Slav

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Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their phone some movie, you will know that you worked on that chip which streamed the movie so seamlessly […]

Feb 8

How to Decouple Threads in SystemVerilog

Posted by Cristian Slav

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Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not always the case. In this article I am presenting one way of killing a task via process.kill() API […]

Sep 21

SystemVerilog Tip: How to Do Logging in UVM

Posted by Cristian Slav

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UVM comes with a great messaging system which can be easily controlled with simulator commands. Some of these commands are making use of an ID which can be assign to a message. Unfortunately, UVM does not allow us to assign multiple IDs to the same message. In this post I will present why assigning multiple […]

Jul 22

How to Handle Data Coming From Parallel Threads

Posted by Cristian Slav

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It is quite common for a DUT to have two or more interfaces from which, independent monitors, will send data to a scoreboard in the same simulation time. Because this is done from parallel threads, the order in which the data arrived in our scoreboard is random. If the order in which the data is […]

Mar 7

How to Use UVM Callbacks With Configuration Fields

Posted by Cristian Slav

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In computer programming, a callback is basically a function which you can pass to some existing code to be called at some specific event. UVM offers all the pieces of the puzzle to easily implement callbacks in any verification environment in just a few simple steps. In this post I will show you how I […]

Sep 1

How to Access a Protected Property or Method in SystemVerilog

Posted by Cristian Slav

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You might get into a scenario in which you really need to access a protected property or maybe a protected method from some SystemVerilog class. If override is not a solution for you then you might get away with this trick: create a subclass and via static functions access any properties from a reference which […]

Feb 15

SystemVerilog: How To Hide Your Fields So That Anyone Can Find Them

Posted by Cristian Slav

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In this post I will talk about how I am using the OOP concept of Variable Shadowing to make the user interaction with VIPs much easier. Every now and then I am asked to build an agent to be used by the entire team for some communication protocol, like the interface for accessing the registers […]

Sep 28

SystemVerilog: Tips And Tricks When Working With Queues

Posted by Cristian Slav

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In this post I put together a few tips and tricks I’ve came across over the years related to SystemVerilog queues. Access the last element of a queue For a long time I was accessing the last element in a queue the “normal” way – using the computed index of that last element: 1my_value = […]

Jun 14

SystemVerilog: How To Handle Reset In UVM (part 2)

Posted by Cristian Slav

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A while back I wrote an article about how to handle the reset in an UVM agent component.Someone asked a very good question: How about handling the reset in the scoreboard? In this article I will share with you my way of handling the reset in a verification environment. Let’s say that we have a […]