UVM registers model comes with a very simple and quite useful feature: it supports more than one reset signal. Let’s say that we have an RTL with 3 input signals: Inside this RTL, among others, we have a register called CTRL, with three fields, affected differently by the reset signals: We can see in the […]
SystemVerilog
The in-line constraints in SystemVerilog are implemented by the class.randomize() with {…} syntax which basically allows you do add additional constraints over the generation of some field from some class. I’ll show you a very common mistake which engineers are doing with this feature. Let’s say that we have a sequence item with some integer […]
Even if it sounds like something quite simple, handling reset in an UVM agent is not that trivial when it comes to actual implementation.In this post I will present a generic mechanism for handling reset which can be reused in any UVM agent. Let’s consider that we have an UVM agent with the following architecture: […]
I recently discovered that 2012 SystemVerilog standard introduced an extremely awesome feature called Interface Classes. I’ll try to explain what it does as simple as possible: In an interface class you can declare what functions you want a class to have. A class can implement an interface class and when doing that it must provide […]
When we say “debugging” the first instinct is to associate it with something like a scoreboard or a monitor but quite often a fair amount of time will be spent in debugging the sequences. The code inside the sequences can easily become huge and complicated. If you have sequences running on multiple threads, fighting for […]
Creating data masks is a very common task in the life of a verification engineer. While doing that I came across one very interesting gotcha. I wanted to obtain a data mask for the second least significant byte of a word: 32’h0000FF00 Pretty simple stuff, right? Here is the code that I did for this: […]
Let’s assume that we need to implement a check for a DUT output signal like a FIFO full interrupt with the following behavior: it becomes 1 when a FIFO is full, it becomes 0 only when the interrupt is cleared (e.g. sticky interrupt). Seams pretty simple, right? In my experience with junior verification engineers I […]
It is a well known fact that debugging, not development, takes most of the time when verifying an DUT (Device Under Test). This is true for all software development branches, not just in hardware verification. Beside the simulators, IDEs, machine clusters and any other thing that a company can invest in I believe that the […]
One too many times I’ve seen great verification engineers, experts in ‘e’ language programming, afraid of moving towards SystemVerilog. Their fears covered the full spectrum: from online myths to extremely well founded arguments. Regardless of how well or not is the argument, times are changing and we need to keep up with the technologies. One […]
In a previous post I described all the steps that you have to take in order to start a register model using uvm_reg library. One very nice feature of uvm_reg is the register callback extensions. This is just a fancy name for saying that you can set some action to be executed when a register […]