In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common scoreboard...
Category - UVM
Cristian Slav
Verification Is All About … Trust
Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their...
How to Decouple Threads in SystemVerilog
Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not...
