Category - UVM

SystemVerilog UVM uvm_reg

Why Does uvm_reg::read() Return Wrong Data?

In this post, I will highlight the reason and a simple solution for a common problem: the data returned by the uvm_reg::read() task is not the same as the data returned by the DUT. If you want to jump directly to the...

Cristian Slav

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SystemVerilog UVM

How To Check if the DUT Is Stuck

Cristian Slav

SystemVerilog UVM uvm_reg Verification

Course: Design Verification with SystemVerilog/UVM

I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how...

Cristian Slav

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'e' Language SystemVerilog UVM uvm_reg Verification vr_ad

Verification Is All About … Trust

Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their...

Cristian Slav

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SystemVerilog UVM

How to Decouple Threads in SystemVerilog

Cristian Slav

2023-02-08

SystemVerilog UVM

SystemVerilog Tip: How to Do Logging in UVM

Cristian Slav

2022-09-21