In this post, I will highlight the reason and a simple solution for a common problem: the data returned by the uvm_reg::read() task is not the same as the data returned by the DUT. If you want to jump directly to the...
Category - uvm_reg
Cristian Slav
Verification Is All About … Trust
Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their...
SystemVerilog: How To Model Multiple Reset Signals in UVM Registers
UVM registers model comes with a very simple and quite useful feature: it supports more than one reset signal. Let’s say that we have an RTL with 3 input signals: Inside this RTL, among others, we have a register...
