I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how...
Category - uvm_reg
Cristian Slav
SystemVerilog: How To Model Multiple Reset Signals in UVM Registers
UVM registers model comes with a very simple and quite useful feature: it supports more than one reset signal. Let’s say that we have an RTL with 3 input signals: Inside this RTL, among others, we have a register...
How to Use Register Callbacks in uvm_reg Library
In a previous post I described all the steps that you have to take in order to start a register model using uvm_reg library. One very nice feature of uvm_reg is the register callback extensions. This is just a fancy...
