Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their phone some movie, you will know that you worked on that chip which streamed the movie so seamlessly […]
UVM registers model comes with a very simple and quite useful feature: it supports more than one reset signal. Let’s say that we have an RTL with 3 input signals: Inside this RTL, among others, we have a register called CTRL, with three fields, affected differently by the reset signals: We can see in the […]
In a previous post I described all the steps that you have to take in order to start a register model using uvm_reg library. One very nice feature of uvm_reg is the register callback extensions. This is just a fancy name for saying that you can set some action to be executed when a register […]
In this post I will describe all the steps I take to startup the uvm_reg register model. If you do things differently please share your view in the comments section below. If you want to see what is the equivalent of this in e language, with vr_ad library, have a look at this article: How […]
