I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“.
In this course, you’ll delve into two crucial areas:
- UVM Library: Uncover all its features, secrets, and how they can be applied effectively in verification environments.
- Verification Environment Creation: Learn the step-by-step process of building a robust verification environment from the ground up using UVM.
Course Objectives:
Throughout this course, we’ll guide you through the development of a verification environment, meticulously designed using the UVM library. Each tutorial will introduce new functionalities, demonstrating the UVM features necessary for each phase of our comprehensive project.
We’ll leverage the EDA Playground platform to develop our verification environment. By the end of the course, our final project will encompass over 5000 lines of code, providing a substantial showcase of your acquired skills and knowledge.
By the end of this course, you will master:
- Building UVM agents and understanding their roles
- Modeling design registers using the UVM library
- Setting up a Device Under Test (DUT) within a verification environment
- Verifying the outputs of a DUT to ensure accuracy and functionality
- Implementing functional coverage in SystemVerilog to achieve thorough verification
- Writing and executing random tests to cover a wide range of scenarios
- Employing advanced debugging techniques to identify and resolve issues
- Exploring and utilizing hidden features of the UVM library to enhance your projects
The skills you gain from this course will not only prepare you for entry or junior-level verification engineer job interviews but will also ensure you are productive and effective from day one in your new role.