Cristian Slav
In this post I will describe all the steps I take to startup the uvm_reg register model. If you do things differently please share your view in the comments section below. If you want to see what is the equivalent of...
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How to Use Register Callbacks in uvm_reg Library
In a previous post I described all the steps that you have to take in order to start a register model using uvm_reg library. One very nice feature of uvm_reg is the register callback extensions. This is just a fancy...
How To Code Efficiently In SystemVerilog Without AOP
One too many times I’ve seen great verification engineers, experts in ‘e’ language programming, afraid of moving towards SystemVerilog. Their fears covered the full spectrum: from online myths to...
Specman Secrets – Inline Text Expansion
Even though ‘e’ language documentation is quite well written, there are still some stuff either not described in the specifications, or described in just a few words. That’s a pity since, over time, I...
Debugging Tip: Always Remember The Cause
It is a well known fact that debugging, not development, takes most of the time when verifying an DUT (Device Under Test). This is true for all software development branches, not just in hardware verification. Beside...
How to Verify a DUT Output Signal
Let’s assume that we need to implement a check for a DUT output signal like a FIFO full interrupt with the following behavior: it becomes 1 when a FIFO is full, it becomes 0 only when the interrupt is cleared (e.g...