Even though ‘e’ language documentation is quite well written, there are still some stuff either not described in the specifications, or described in just a few words. That’s a pity since, over time, I found out a lot of useful undocumented features of ‘e’ language.
The first one that I want to share with you is described with just a couple of words as “Inline Text Expansion”.
It allows you to write a string on multiple lines without any backslash (\) and it allows you to insert values in the string directly.
Here is an example:
var my_number : uint = 10;
var my_strings : list of string = << #:
this is the first line
my number is <(my_number)>
end #;
print my_strings;
The output for this code is this:
this is the first line
my number is 10
Pretty cool, right?
You are probably thinking: where in the hell will I make use of this?
Well, the only place I found this very useful is when I had to build macros “as computed”. It makes the macro definition much more readable:
define
return str_join(<< #:
{
extend <(str_upper(
keep data_width == <(
};
};
end #, "");
};
Calling the macro will look like this:
set_data_width in APB to 16;
set_data_width in AXI to 32;
The resulting code will be:
extend APB_DEFAULT cfs_apb_agent_config {
keep data_width == 16;
};
extend AXI_DEFAULT cfs_axi_agent_config {
keep data_width == 32;
};
Hope you found this useful!
If you want to gain an in-depth knowledge on how to do module level verification using SystemVerilog and UVM language then checkout my Udemy course called “Design Verification with SystemVerilog/UVM“

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