Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their phone some movie, you will know that you worked on that chip which streamed the movie so seamlessly […]
Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not always the case. In this article I am presenting one way of killing a task via process.kill() API […]
Verifying RTL updatable registers (e.g. status registers) can be very difficult due to factors like slight desynchronization between model and DUT or different sampling points for the register value. Register reads in the out-of-synch window produce false errors which are a nightmare to handle in the verification environment. Luckily, the vr_ad library comes with a […]
UVM comes with a great messaging system which can be easily controlled with simulator commands. Some of these commands are making use of an ID which can be assign to a message. Unfortunately, UVM does not allow us to assign multiple IDs to the same message. In this post I will present why assigning multiple […]
In ‘e’ language events are heavily used for all kinds of jobs, from coverage collection, to TCMs synchronization or even passing data between two entities (a reminiscence from the times when the concept of ports was not yet introduced). The syntax for declaring an event in ‘e’ is pretty straight forward: One of the most […]
It is quite common for a DUT to have two or more interfaces from which, independent monitors, will send data to a scoreboard in the same simulation time. Because this is done from parallel threads, the order in which the data arrived in our scoreboard is random. If the order in which the data is […]
In this post I will describe all the steps I take to startup the vr_ad register model, implemented in e language. If you do things differently please share your view in the comments section below. If you want to see what is the equivalent of this in SystemVerilog, with UVM library, have a look at this […]
‘e’ language is an Aspect Oriented Programming (AOP) language with a lot of awesome features. One of this features is the ability to extend methods with one of the following statements: is also is first is only In this article we’ll see the strange way in which Specman’s return statement behaves with this very nice […]
In computer programming, a callback is basically a function which you can pass to some existing code to be called at some specific event. UVM offers all the pieces of the puzzle to easily implement callbacks in any verification environment in just a few simple steps. In this post I will show you how I […]
You might get into a scenario in which you really need to access a protected property or maybe a protected method from some SystemVerilog class. If override is not a solution for you then you might get away with this trick: create a subclass and via static functions access any properties from a reference which […]
