Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their phone some movie, you will know that you worked on that chip which streamed the movie so seamlessly […]
Verifying RTL updatable registers (e.g. status registers) can be very difficult due to factors like slight desynchronization between model and DUT or different sampling points for the register value. Register reads in the out-of-synch window produce false errors which are a nightmare to handle in the verification environment. Luckily, the vr_ad library comes with a […]
In this post I will describe all the steps I take to startup the vr_ad register model, implemented in e language. If you do things differently please share your view in the comments section below. If you want to see what is the equivalent of this in SystemVerilog, with UVM library, have a look at this […]
