SystemVerilog

You are here: Home / Archive by Category "SystemVerilog" / Page 3

How to Use Register Callbacks in uvm_reg Library

Posted by

In a previous post I described all the steps that you have to take in order to start a register model using uvm_reg library. One very nice feature of uvm_reg is the register callback extensions. This is just a fancy name for saying that you can set some action to be executed when a register […]

How to Startup uvm_reg SystemVerilog Library

Posted by

In this post I will describe all the steps I take to startup the uvm_reg register model. If you do things differently please share your view in the comments section below. If you want to see what is the equivalent of this in e language, with vr_ad library, have a look at this article: How […]

Page 3 of 3 1 2 3