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Mar 11

Course: Design Verification with SystemVerilog/UVM

Posted by Cristian Slav

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I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how they can be applied effectively in verification environments. Verification Environment Creation: Learn the step-by-step process of building a robust verification environment from the ground up using […]

Jul 18

Verification Is All About … Trust

Posted by Cristian Slav

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Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their phone some movie, you will know that you worked on that chip which streamed the movie so seamlessly […]

Feb 8

How to Decouple Threads in SystemVerilog

Posted by Cristian Slav

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Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not always the case. In this article I am presenting one way of killing a task via process.kill() API […]

Sep 21

SystemVerilog Tip: How to Do Logging in UVM

Posted by Cristian Slav

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UVM comes with a great messaging system which can be easily controlled with simulator commands. Some of these commands are making use of an ID which can be assign to a message. Unfortunately, UVM does not allow us to assign multiple IDs to the same message. In this post I will present why assigning multiple […]