In this post, I will highlight the reason and a simple solution for a common problem: the data returned by the uvm_reg::read() task is not the same as the data returned by the DUT. If you want to jump directly...
In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common...
‘e’ language is a very powerful language which allows us to make incredible things with its native syntax. It is difficult to reach a point in which you want to do something not supported by the...
I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets...
Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching...
Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not...
Verifying RTL updatable registers (e.g. status registers) can be very difficult due to factors like slight desynchronization between model and DUT or different sampling points for the register value. Register reads in...
UVM comes with a great messaging system which can be easily controlled with simulator commands. Some of these commands are making use of an ID which can be assign to a message. Unfortunately, UVM does not allow us to...
In ‘e’ language events are heavily used for all kinds of jobs, from coverage collection, to TCMs synchronization or even passing data between two entities (a reminiscence from the times when the concept of...
It is quite common for a DUT to have two or more interfaces from which, independent monitors, will send data to a scoreboard in the same simulation time. Because this is done from parallel threads, the order in which...
In this post I will describe all the steps I take to startup the vr_ad register model, implemented in e language. If you do things differently please share your view in the comments section below. If you want to...
‘e’ language is an Aspect Oriented Programming (AOP) language with a lot of awesome features. One of this features is the ability to extend methods with one of the following statements: is also is first is...
In computer programming, a callback is basically a function which you can pass to some existing code to be called at some specific event. UVM offers all the pieces of the puzzle to easily implement callbacks in any...
You might get into a scenario in which you really need to access a protected property or maybe a protected method from some SystemVerilog class. If override is not a solution for you then you might get away with this...
In this post I will talk about how I am using the OOP concept of Variable Shadowing to make the user interaction with VIPs much easier. Every now and then I am asked to build an agent to be used by the entire team for...
In this post I will talk about how to create a complex structure of SystemC modules and how to connect them so that information can be passed between them safely. Here is a list of content if you want to jump to a...
In this post I put together a few tips and tricks I’ve came across over the years related to SystemVerilog queues. Access the last element of a queue For a long time I was accessing the last element in a queue the...
Cristian Slav