In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common scoreboard architecture has the following...

‘e’ language is a very powerful language which allows us to make incredible things with its native syntax. It is difficult to reach a point in which you want to do something not supported by the language. But, if you do, ‘e’...

I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how they can be applied effectively...

Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their phone some movie, you will know...

Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not always the case. In this article I...