Cristian Slav
Verifying RTL updatable registers (e.g. status registers) can be very difficult due to factors like slight desynchronization between model and DUT or different sampling points for the register value. Register reads in...
SystemVerilog Tip: How to Do Logging in UVM
UVM comes with a great messaging system which can be easily controlled with simulator commands. Some of these commands are making use of an ID which can be assign to a message. Unfortunately, UVM does not allow us to...
How to Miss Events in Specman
In ‘e’ language events are heavily used for all kinds of jobs, from coverage collection, to TCMs synchronization or even passing data between two entities (a reminiscence from the times when the concept of...
How to Handle Data Coming From Parallel Threads
It is quite common for a DUT to have two or more interfaces from which, independent monitors, will send data to a scoreboard in the same simulation time. Because this is done from parallel threads, the order in which...
How to Startup vr_ad e Library
In this post I will describe all the steps I take to startup the vr_ad register model, implemented in e language. If you do things differently please share your view in the comments section below. If you want to...
The Strange Ways of Specman’s Return Statement
‘e’ language is an Aspect Oriented Programming (AOP) language with a lot of awesome features. One of this features is the ability to extend methods with one of the following statements: is also is first is...
How to Use UVM Callbacks With Configuration Fields
In computer programming, a callback is basically a function which you can pass to some existing code to be called at some specific event. UVM offers all the pieces of the puzzle to easily implement callbacks in any...
How to Access a Protected Property or Method in SystemVerilog
You might get into a scenario in which you really need to access a protected property or maybe a protected method from some SystemVerilog class. If override is not a solution for you then you might get away with this...
SystemVerilog: How To Hide Your Fields So That Anyone Can Find Them
In this post I will talk about how I am using the OOP concept of Variable Shadowing to make the user interaction with VIPs much easier. Every now and then I am asked to build an agent to be used by the entire team for...
Learning SystemC: #006 Module Hierarchy And Connectivity
In this post I will talk about how to create a complex structure of SystemC modules and how to connect them so that information can be passed between them safely. Here is a list of content if you want to jump to a...
SystemVerilog: Tips And Tricks When Working With Queues
In this post I put together a few tips and tricks I’ve came across over the years related to SystemVerilog queues. Access the last element of a queue For a long time I was accessing the last element in a queue the...
Learning SystemC: #005 Signal Channels
In this post I will talk about SystemC signal channels. These channels help us establish an easier data synchronization. Here is a list of content if you want to jump to a particular subject: 1. What Are Signal Channels...