In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common scoreboard...
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Cristian SlavThe Power of “define … as computed”
‘e’ language is a very powerful language which allows us to make incredible things with its native syntax. It is difficult to reach a point in which you want to do something not supported by the language...
Course: Design Verification with SystemVerilog/UVM
I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how...
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Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their...
Latest articles
SystemVerilog: How To Handle Reset In UVM (part 1)
Even if it sounds like something quite simple, handling reset in an UVM agent is not that trivial when it comes to actual implementation.In this post I will present a generic mechanism for handling reset which can be...
How To Check if the DUT Is Stuck
In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common scoreboard...
SystemVerilog: Tips And Tricks When Working With Queues
In this post I put together a few tips and tricks I’ve came across over the years related to SystemVerilog queues. Access the last element of a queue For a long time I was accessing the last element in a queue the...
SystemVerilog Tip: How to Do Logging in UVM
UVM comes with a great messaging system which can be easily controlled with simulator commands. Some of these commands are making use of an ID which can be assign to a message. Unfortunately, UVM does not allow us to...
Learning SystemC: #001 Data Types
In this post I will talk about the data types part of the SystemC library. Here is a list of content if you want to jump to a particular subject: 1. Fixed-precision integer types 1.1 sc_int...
UVM: How to Pass a Virtual Interface from Testbentch to Environment
Connecting a verification environment with a DUT is not a straight forward task for someone new to UVM and the purpose of this post is to give a quick tutorial on how to do it fast and correctly. Let’s assume that...
Debugging Tip: Look At The Bubbles
When we say “debugging” the first instinct is to associate it with something like a scoreboard or a monitor but quite often a fair amount of time will be spent in debugging the sequences.The code inside the...
SystemVerilog: How To Handle Reset In UVM (part 2)
A while back I wrote an article about how to handle the reset in an UVM agent component.Someone asked a very good question: How about handling the reset in the scoreboard? In this article I will share with you my way of...
How to Use Register Callbacks in uvm_reg Library
In a previous post I described all the steps that you have to take in order to start a register model using uvm_reg library. One very nice feature of uvm_reg is the register callback extensions. This is just a fancy...
How to Handle Data Coming From Parallel Threads
It is quite common for a DUT to have two or more interfaces from which, independent monitors, will send data to a scoreboard in the same simulation time. Because this is done from parallel threads, the order in which...