Cristian Slav
In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common scoreboard...
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The Power of “define … as computed”
‘e’ language is a very powerful language which allows us to make incredible things with its native syntax. It is difficult to reach a point in which you want to do something not supported by the language...
Course: Design Verification with SystemVerilog/UVM
I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how...
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How To Check if the DUT Is Stuck
In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common scoreboard...
The Power of “define … as computed”
‘e’ language is a very powerful language which allows us to make incredible things with its native syntax. It is difficult to reach a point in which you want to do something not supported by the language...
Course: Design Verification with SystemVerilog/UVM
I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how...
Verification Is All About … Trust
Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their...
How to Decouple Threads in SystemVerilog
Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not...
The Hidden Feature of vr_ad: Gray Zone Comparison
Verifying RTL updatable registers (e.g. status registers) can be very difficult due to factors like slight desynchronization between model and DUT or different sampling points for the register value. Register reads in...
Layout C (3 columns)
How To Check if the DUT Is Stuck
In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common scoreboard...
The Power of “define … as computed”
‘e’ language is a very powerful language which allows us to make incredible things with its native syntax. It is difficult to reach a point in which you want to do something not supported by the language...
Course: Design Verification with SystemVerilog/UVM
I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how...
Verification Is All About … Trust
Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their...
How to Decouple Threads in SystemVerilog
Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not...
The Hidden Feature of vr_ad: Gray Zone Comparison
Verifying RTL updatable registers (e.g. status registers) can be very difficult due to factors like slight desynchronization between model and DUT or different sampling points for the register value. Register reads in...
Layout C (4 columns)
How To Check if the DUT Is Stuck
In this article I am describing one technique (out of many) to catch the scenario in which a DUT (Device Under Test) gets stuck, no longer outputting any information on some particular bus. A very common scoreboard...
The Power of “define … as computed”
‘e’ language is a very powerful language which allows us to make incredible things with its native syntax. It is difficult to reach a point in which you want to do something not supported by the language...
Course: Design Verification with SystemVerilog/UVM
I’ve created a course on Udemy called “Design Verification with SystemVerilog/UVM“. In this course, you’ll delve into two crucial areas: UVM Library: Uncover all its features, secrets, and how...
Verification Is All About … Trust
Dear future verification engineer, You are about to start a very privileged career. You will have the opportunity to see your work all around you. When you’re in the subway and you see someone watching on their...
How to Decouple Threads in SystemVerilog
Killing a task in SystemVerilog is relatively easy using the kill() method from the process API. Usually, when we kill a task, we also want to terminate all of its “sub-tasks” it called. But this is not...
The Hidden Feature of vr_ad: Gray Zone Comparison
Verifying RTL updatable registers (e.g. status registers) can be very difficult due to factors like slight desynchronization between model and DUT or different sampling points for the register value. Register reads in...
SystemVerilog Tip: How to Do Logging in UVM
UVM comes with a great messaging system which can be easily controlled with simulator commands. Some of these commands are making use of an ID which can be assign to a message. Unfortunately, UVM does not allow us to...
How to Miss Events in Specman
In ‘e’ language events are heavily used for all kinds of jobs, from coverage collection, to TCMs synchronization or even passing data between two entities (a reminiscence from the times when the concept of...
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